DesignCon 2013 Analysis and Decomposition of Duty Cycle Distortion from Multiple Sources

In jitter analysis, jitter is decomposed into components, most of which are uniquely defined. However, some components use terminology that has caused confusion. For example, terms such as duty-cycle distortion (DCD) in data signals, DCD in clock signals, pulse width jitter (PWJ), and periodic jitter (PJ) at half of the data rate have meanings that depend on application, standards specification, and even measurement methods. In some situations, these terms are redundant. In others, these terms describe fundamentally different mechanisms and behaviors. In this paper, we provide a review of these jitter components. We explore the origins of these terms, their definitions, and intended goals. We demonstrate cases where these components interact and produce effects that may be mischaracterized as different jitter components. We provide simulation and laboratory correlation for these cases, as well as guidelines for accurate identification and decomposition of the source jitter components. Authors Biography Dr. Daniel Chow is a Principal Signal Integrity Engineer at Altera Corporation. His responsibilities include defining design, testing, and validation methodologies for signal integrity, power integrity, and jitter analysis in high-speed components. Specifically, he is responsible for developing Altera’s knowledge base on jitter-related issues. Before joining the industry, he was a research physicist with the U.S. Department of Energy. Dr. Chow received his Ph.D. from the University of California, Davis. Shufang Tian is a Member of Technical Staff at Altera Corporation. She is responsible for Altera’s high speed transceiver characterization. She received her master from University of Southern California. Yanjing Ke is a Sr. Member of Technical Staff at Altera Corporation. She is responsible for Altera’s high speed transceiver analog circuit design. She received her Master’s degree from Tsing Hua University and Florida International University. Kaiyu Ren is a Member of Technical Staff at Altera Corporation. She works on Altera high speed Transceiver characterization for the past 13 years. Her scope of work includes transceiver jitter, PDN, signal integrity. She received her Master’s degree from University of Toledo. Introduction In recent decades, jitter analysis has matured in terms of theory, simulation, and measurement. Most data communication standards specifications include detailed requirements for jitter. However, as data rates increase, jitter budgets decrease. Jitter components that previously had relatively small contributions are now significant. Similarly, as system architectures increase in complexity, new types of jitter components were defined to describe the interactions of the system’s components. We review the various ways jitter is broken down into components, depending on standards specifications and physics-based behavior. We examined some of the newer terminology for jitter components, such as non-periodic bounded, uncorrelated jitter (BUJ or NPBUJ), sub-rate jitter (SRJ), duty-cycle distortion (DCD) in data signals, DCD in clock signals, periodic jitter (PJ) at half of data rate (f/2), correlated jitter, uncorrelated jitter, and pulse width jitter (PWJ). We compared the definitions of these jitter components and showed redundancy under specific situations, thereby causing confusion among end users. We demonstrate techniques for resolving redundancies and methods for better characterization of device performance. Survey of Jitter Components There exist a wealth of literature on the definitions of common jitter components such as total jitter (TJ), random jitter (RJ), deterministic jitter (DJ), periodic or sinusoidal jitter (PJ or SJ), data-dependent jitter (DDJ), and inter-symbol interference (ISI) [1]. We reviewed some jitter components that are less common and/or require a more detailed description. Data-Dependent Duty Cycle Distortion Signal rise and fall times may not identical due to mismatches in the circuit components. As a result, the length of a “1” is different than the length of a “0”, but only when adjacent to a transition edge. This is defined as data-dependent duty cycle distortion (Data DCD). Most jitter separation software refers to behavior simply as DCD, which causes confusion with half rate clock DCD described in the next section. For singleended signals, Data DCD can be significant. For differential signals, rise/fall time mismatch cancels out such that Data DCD can be negligibly small. Half-Rate Clock Duty Cycle Distortion Transceiver designs typically use a half-rate architecture. Stress in the clock paths can cause mismatch in the rise and fall times of the half-rate clock and duty cycle distortion (f/2 DCD, where f is the data rate). As a result, “even” bits launched on a rising clock edge have a different length than “odd” bits launched on a falling clock edge. Sub-Rate Jitter Occasionally, jitter can be correlated to a sub-rate of a data pattern, known as sub-rate jitter (SRJ) [2]. SRJ may be caused by muxing architectures such that jitter events occur at a frequency which is an integer divisor of the data pattern repetition frequency. Bounded, Uncorrelated Jitter For jitter with behaviors that are uncorrelated to the data pattern but do not fit the definitions of RJ and PJ, they are classified as bounded, uncorrelated jitter (BUJ) or nonperiodic, bounded, uncorrelated jitter (NPBUJ). Typically, BUJ describes jitter sources extrinsic to the data transmission channel, such as crosstalk or power supply-induced jitter (PSIJ) [3, 4]. Uncorrelated Total Jitter Some communication standards decompose TJ into a component which is dependent on data (DDJ) and a component which is uncorrelated to data, sometimes referred to as uncorrelated total jitter (UTJ) [5, 6] typically defined to consist of RJ, PJ, and BUJ. Time Interval Error, Pulse Width Jitter Most standards specifications define jitter as the difference between the ideal and the actual times of a transition, or time interval error (TIE). Typically, the ideal time is given by a clock signal, either recovered or forwarded. Some standards include jitter components measured using a previous transition edge in the same signal as a reference. Typically, the previous edge is one bit earlier, thus this type of measurement is referred to as pulse width jitter (PWJ) [5]. In PCI Express 3.0, all UTJ components can be measured as a TIE or a PWJ. One particular application of PWJ is in the SFF-8431 standard, defined as data-dependent pulse width shrinkage (DDPWS) [6]. DDPWS aims to find the narrowest pulse width within only DDJ and excluding any contribution from UTJ components. Interactions of Jitter Components Some jitter components share similar terminology or descriptions, but have independent causes and behavior. In some cases, there exists partial or total redundancy between jitter components depending on conditions, thus creating confusion with end users. In particular, we studied the interactions of Data DCD, f/2 DCD, and DDPWS. We demonstrated that in some situations, the different jitter components have additive or subtractive effects, thus compounding, masking or canceling the contributions of each component. Data DCD and f/2 DCD Figure 1 shows an eye diagram with only rise and fall time mismatch causing Data DCD. The data rate is 10.3125 Gb/s, the data pattern is PRBS 2 7 −1, and the single-ended output is 600 mV p-p. The intersections of rising and falling edges are offset vertically such that rising and falling edges cross the voltage threshold at different times, with rising edges arriving earlier and falling edges arriving later. Standard jitter separation analysis finds that Data DCD is 6 ps. Figure 1: Eye diagram of signal with Data DCD. Through internal settings in the test chip, we stressed the half-rate clock to produce f/2 DCD (Figure 2). Similar to Figure 1, the intersection of rising and falling edges is offset vertically. Additionally, we see that two distinct sets of rising and falling edges, separated by approximately 18 ps, creating the appearance of “double crossings.” Figure 2: Eye diagram of signal with Data DCD and f/2 DCD. It is important to note that the definition of an eye diagram is the superposition of all bits. For some equivalent-time sampling scopes, eye diagram measurements are triggered externally. If the trigger frequency is an odd divisor of the data rate, the eye diagram will be aligned by alternating odd and even bits, resulting in an eye diagram similar to Figure 2. However, if the trigger frequency is an even divisor of the data rate, the eye diagram will be aligned only by even bits (or only by odd bits). As a result, a specific “eye” will consist of only even bits or only odd bits. In this situation, f/2 DCD will cause adjacent eye diagrams to have different widths, resulting in a “big eye/small eye” behavior shown in Figure 3. The difference in widths between a “big eye” and a “small eye” is approximately 36 ps, which is twice the separation of the double crossings. Figure 3: “Big eye/small eye” behavior from sampling scope with even divisor trigger. From Figure 2, jitter separation analysis finds Data DCD to be 5.54 ps, which is consistent with Figure 1. However, most jitter separation techniques do not address f/2 DCD. Because f/2 DCD lengthens or shortens alternating bits in rapid succession, it is behaviorally similar to a high frequency PJ near f/2, the jitter Nyquist frequency. Also, because the data pattern is an odd number of bits in length, any given bit in the pattern will alternate between being an even bit or an odd bit in consecutive repetitions of the pattern. Therefore, f/2 DCD is uncorrelated to the data pattern in this case and behaves like SRJ. However, most jitter separation techniques do not address SRJ either. Thus, conventional jitter separation techniques categorize f/2 DCD as PJ. Comparing with Figure 1, we see that PJ is increased from 2.82 ps to 19.45 ps, which is consistent with the separation of the double crossings. However, for a data pattern that is an even number of bits in length, any given bit in the pattern will always be an even or odd bit in every repetition of the pattern. Thus, we expect f/2 DCD to manifest as DDJ in data patterns with an even number of bits in length. We demonstrated this very easily by manually configuring the oscilloscope to treat the PRBS 2 7 −1 pattern as being 254 bits long, which is twice the normal length and an even number. Because the signal did not change, DDJ due to ISI and Data DCD cannot change. However, by treating the pattern as being 254 bits long, we effectively “unfold” the PRBS pattern such that the first instance of the pattern is launched by an even (or odd) bit and the second instance of the pattern is launched by an odd (or even) bit. Therefore, f/2 DCD is effectively correlated to the 254-bit long data pattern, resulting in f/2 DCD being categorized as DDJ. Figure 4: Eye diagram of signal with Data DCD and f/2 DCD with oscilloscope configured for 254 bits. Comparing Figure 4 with Figure 2, we see that, while the eye diagrams are identical, DDJ increased from 11.93 ps to 29.58 ps and PJ decreased from 19.45 ps to 1.38 ps. The change in both DDJ and PJ is approximately 18 ps, demonstrating that f/2 DCD was “resorted” from PJ to DDJ. We can visualize this effect more intuitively by examining a plot of DDJ vs. the bit number. Figure 5 shows the DDJ vs. bit for the measurement treating the PRBS pattern as 127 bits long. All UTJ is averaged out, including f/2 DCD. We see that rising edges (red dots) are on average earlier than falling edges (blue dots), indicating rise time is faster than fall time, as expected. The average difference in DDJ between rising and falling edges is 5.5 ps, as expected. Figure 5: DDJ vs. bit # for 127-bit long pattern. In contrast, Figure 6 shows the DDJ vs. bit for treating the PRBS pattern as 254 bits long. Despite the pattern being simply two instances of the same PRBS pattern, the DDJ of the first instance (bits 1 to 127) is completely different from the DDJ of the second instance (bits 128 to 254). We see that rising edges (for both odd and even bits as well as both first and second instances of the PRBS pattern) are consistently earlier than their corresponding falling edges, indicating rise time is faster than fall time. The average difference in DDJ between rise and fall times is 5.5 ps, as expected. Additionally, we see that even bits arrive consistently earlier than odd bits, indicating f/2 DCD such that even bits are longer than odd bits. The average difference in DDJ between odd and even bits is 18 ps, as expected. Figure 6: DDJ vs. bit # for 254-bit long pattern. Degeneracy of Data DCD and f/2 DCD A common method to quantify f/2 DCD is measuring a clock-like “1010” data pattern. For a signal with no Data DCD, measuring the difference in length between ones and zeros accurately captures f/2 DCD. However, if Data DCD is present, measuring “1010” will capture a combination of f/2 DCD and Data DCD, because all even bits are launched with a rising edge and all odd bits are launched with a falling edge. We configured the test chip to transmit a “1010” pattern. At 10.3125 Gb/s, the ideal UI is approximately 97 ps. From the previous section, we know that rising edges arrive approximately 5.5 ps faster than the falling edges. From Figure 6, we know that even bits are approximately 18 ps longer than odd bits. In this pattern, “1’s” are even and “0’s” are odd. As a result, the width of a “1” is given by ps 5 . 120 DCD 2 DCD Data UI Even 1     f , t t t T , Eq. 1 which is comparable to the measured value of 119 ps (Figure 7). Similarly, the width of a “0” is given by ps 5 . 73 DCD 2 DCD Data UI Odd , 0     f t t t T , Eq. 2 which is comparable to the measured value of 75 ps (Figure 7). Figure 7: Pulse widths of signal with Data DCD and f/2 DCD for “1010” pattern. Next, we reconfigured the device to transmit a “0101” patter such that “0’s” are even and “1’s” are odd (Figure 8). The width of a “0” is now given by ps 5 . 109 DCD 2 DCD Data UI Even , 0     f t t t T , Eq. 3 which is comparable to the measured value of 106 ps. The change in sign for tf/2 DCD is due to the “0” being launched on a falling edge instead of a rising edge. Similarly, the width of a “1” is now given by ps 5 . 84 DCD 2 DCD Data UI Odd , 1     f t t t T , Eq. 4 which is comparable to the measured value of 88 ps. Figure 8: Pulse widths of signal with Data DCD and f/2 DCD for “0101” pattern. We can generalize the interaction of Data DCD and f/2 DCD as follows: DCD 2 DCD Data UI f t t t T    , Eq. 5 where tData DCD is the absolute value of the timing difference between rising and falling edges and tf/2 DCD is the absolute value of the difference in length of even and odd bits. The sign notation for tData DCD and tf/2 DCD is given below in Table 1 for all combinations of even/odd bits and “1’s” and “0’s”. “1” “0” Even + − Odd + − Table 1: Sign notation for Data DCD values in pulse width calculation. “1” “0” Even + + Odd − − Table 2: Sign notation for f/2 DCD values in pulse width calculation. From these examples, we see that a simple “1010” pattern is insufficient to find f/2 DCD if there is rise/fall time mismatch. Data Dependent Pulse Width Shrinkage In optical communications, the electrical-to-optical interface module requires a minimum pulse with in order for the laser to ramp up to full intensity, which is critical for maximum signal transmission distance. Data dependent pulse width shrinkage (DDPWS) is defined in the SFF-8431 standard [6]. In essence, it is finding the narrowest pulse in the PRBS 2 9 −1 compliance test pattern (511 bits long), but taking only into account DDJ. Since the compliance test pattern length is odd, f/2 DCD is uncorrelated and averaged out in the measurement. Figure 9 shows DDPWS compliance test methodology applied to a PRBS 2 7 −1, which is also odd in length for proof of principle. The largest value of DDPWS is 10.86 ps at bit 26 in the pattern. Figure 9: SFF-8431 DDPWS compliance test methodology applied to PRBS 2 7 −1 (127 bits long). However, in application, f/2 DCD can significantly impact DDPWS. We can determine that impact by performing the compliance test on an even-length pattern. Again, we simply configure the oscilloscope to treat the PRBS pattern as being twice as long (254 bits). As with our DDJ analysis, this process “unfolds” the DDPWS into odd and even bits. Figure 10 shows DDPWS vs. bit for 254-bit long patterns. Bit 26 now shows DDPWS of −6.6 ps due to the fact that it is an even bit and longer than the ideal UI (negative shrinkage). The corresponding bit in the second instance (bit 253) shows DDPWS of 28.3 ps due to the fact that it is an odd bit and shorter than the ideal UI (more shrinkage). The average of these two values is 10.86 ps, which is the DDPWS for the same bit in Figure 9, thus demonstrating that the DDPWS compliance test averages out f/2 DCD contributions. Figure 10: SFF-8431 DDPWS compliance test methodology applied to PRBS 2 7 −1 (254 bits long). The largest DDPWS in Figure 10 occurs at bit 153 with a value of 28.3 ps. In a application, this more closely resembles the worst case DDPWS, which is not captured in the compliance test pattern. Measurement Artifacts Equipment setups can affect timing measurements. Data signals may have a common mode voltage and termination impedance. Most oscilloscopes are terminated to ground and creates contention with the common mode voltage. As a result, most characterization is performed with dc blocking capacitors. Most oscilloscopes have single-ended channel inputs. For characterizing differential signals, the oscilloscope calculates the difference between the positive and negative arms of the signals received separately as singled-ended inputs. Most oscilloscopes offer the timing measurement threshold as a user setting. Typically, it is defaulted to 50% of the signal’s peak-to-peak amplitude. For single-ended signals, 50% is appropriate as a threshold. However, for differential signals, by definition, the threshold is the intersection of the positive and negative arms, such that the difference is 0 volts. For signals that are dc balanced, the 50% threshold is very close to 0 volts. For differential signals with dc imbalance, such as the case with f/2 DCD, the 50% threshold may be significantly different from 0 volts. Figure 11 shows pulse width measurements of a signal with dc imbalance using 50% as a threshold, which is located at −8.7 mV. The positive pulse width is 89 ps and the negative pulse width is 105 ps. Figure 12 shows the same signal measured using 0 mV as a threshold. The positive pulse width is 92 ps and the negative pulse width is 102 ps. Thus, choosing the appropriate timing measurement threshold becomes increasingly important. Figure 11: Pulse widths of signal with Data DCD and f/2 DCD for “0101” pattern with threshold at 50% of signal peak-to-peak. Figure 12: Pulse widths of signal with Data DCD and f/2 DCD for “0101” pattern with threshold at 0 mV. Summary, Conclusions We demonstrated that Data DCD, f/2 DCD, and DDPWS may have unintended interactions depending on conditions such as data pattern and pattern length. We showed debugging techniques for separating Data DCD and f/2 DCD. We demonstrated that DDPWS measurements may neglect f/2 DCD contributions, as well as methods to capture it. We showed that instrument settings may affect the accuracy of the measurements. As data rates increase, jitter budgets become very tight such that every fraction of apicoseconds matters. This paper provides guidelines for clarifying jitter terminology,identifying degeneracy among jitter components, and methodology for jitter debug andseparation. References[1] M.Li, “Jitter, Noise, and Signal Integrity at High-Speed,” Prentice Hall, 2007.[2] http://cp.literature.agilent.com/litweb/pdf/5989-1146EN.pdf.[3] D.Chow, “Analysis of Crosstalk Effects on Jitter in Transceivers,” DesignCon, 2008.[4] S.Sun, K.Ren, D.Chow, W.Ding, T.Hoang, K.Daxer, M.Li, S.Shumarayev, “PDNNoise to Jitter Transfer in High Speed Transceiver,” DesignCon, 2012.[5] PCIe Base 3.0 Specification:http://www.pcisig.com/members/downloads/specifications/pciexpress/PCI_Express_Base_r3.0_v1.0_10Nov10_cb.pdf.[6] SFF-8431 Specifications: ftp://ftp.seagate.com/sff/SFF-8431.PDF.